| Architecture / Microarchitecture | |
| Microarchitecture | Core |
| Processor core ? | Merom-2M |
| Core stepping ? | M0 (QBNT, SLAVG) |
| CPUID | 6FD (QBNT, SLAVG) |
| Manufacturing process | 0.065 micron |
| Data width | 64 bit |
| The number of CPU cores | 2 |
| The number of threads | 2 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 2 x 32 KB 8-way set associative instruction caches 2 x 32 KB 8-way set associative data caches |
| Level 2 cache size ? | 1 MB 4-way set associative shared cache |
| Multiprocessing | Not supported |
| Extensions and Technologies |
|
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